Verification vs Validation in VLSI

The terms Verification and Validation refer to the testing of the design at different stages of the ASIC flow.

ASIC/SoC Verification-

It is the stage in the Chip Development Life Cycle where the design is checked (or verified) for the intended design specifications. It is initiated from the time the design architecture/micro architecture is defined. The objective of verification is to ensure that the functionalities of the design are correct before fabrication of the chip. Simulations are done with RTL and netlists to ensure functionality. Debugging is easy and bugs found at this stage are fixed in the RTL. As once the chip is taped out, any functionality errors would be fatal and cost the worst. The Verification step is considered as very crucial part of design life cycle as any critical bugs in the design not discovered before fabrication would lead to the need of newer processing and hence, increasing the overall cost of design process.

ASIC/SoC Validation-

Validation is the process of testing a manufactured/fabricated chip for its functional and electrical correctness in a characterisation or test and measurements (T&M) laboratory. This is achieved using the silicon chip assembled on the characterisation board, testing board or an evaluation/reference board accompanied with other related component parts of the system design. It is done at the system level. The aim is to validate all parameters of the chip defined by the specification. To qualify the design parameters and modelled parameters, validation of the chip is carried out. It can vary from single feature/interface of the chip to overall features of the design. The testing is carried out involving the software/firmware. The validation team doesn't only involve software engineers but also require highly experienced professional hardware engineers too. The entire process involves validating the chip in a system level environment with actual firmware running the test instructions on the hardware. Debugging is difficult and bugs found at this level can be fixed only by software workarounds.

The confusion between verification and validation has always prevailed as some companies use the term Validation in a wider perspective and classify the processes before and after Silicon availability (fabrication). Verification is also referred to as Pre-Silicon Validation (signifying the testing activities done before the silicon chip is available) and Validation is known as Post-Silicon Validation.

Verification term is usually used for front-end design perspective i.e., the actual verification of the RTL (register transfer logic), which is widely done using System Verilog/Verilog HDLs and using OVM, UVM methodology. The point is to understand that in Verification process, the input to the verification engineer is Specification Sheet and the work is to check if the RTL designer has programmed/designed the given spec appropriately.

Validation term is used only after the silicon is back from fabrication and the team intends to check if the silicon chip is fabricated well and whether the functionalities are operating as it was supposed to be which was specified before it went for fabrication with all debugging and verification done.